[ DevCourseWeb.com ] Udemy - Building Custom AXI Interface Peripherals for ZYNQ Devices

Creation Time	Nov. 17, 2025, 3:57 p.m.
Last Access Time	Jan. 10, 2026, 5:24 p.m.
File Size	3.0 GB
Keywords	Building AXI for - Devices Custom DevCourseWeb Peripherals ZYNQ Interface Udemy com
Total Requests	41
Total Files	131
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~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/37 - Using Vivado Interrupt Template Code P2.mp4 213.6 MB
~Get Your Files Here !/8 - Adding Master Interface/45 - Creating Master Interface with Vivado Template P1.mp4 162.5 MB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/42 - Blinking Effect with Interrupt.mp4 150.7 MB
~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/33 - Adding Interrupt with RTL P2.mp4 149.2 MB
~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/55 - Creating AXIS Master Interface P1.mp4 145.3 MB
~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/49 - Building AXIS Slave Interface P1.mp4 138.8 MB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/36 - Using Vivado Interrupt Template Code P1.mp4 100.1 MB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/23 - Analyzing Signals on ILA Probe.mp4 98.2 MB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/25 - Add Existing RTL Delay Generator P1.mp4 93.7 MB
~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/32 - Adding Interrupt with RTL P1.mp4 90.4 MB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/21 - Other Signals in Slave Lite Interface.mp4 89.6 MB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/27 - Adding Existing RTL Multiplier P1.mp4 83.1 MB
~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/31 - Fundamentals of Interrupt C Application.mp4 80.6 MB
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/7 - Slave Lite Interface without I O Ports P4 Creating C Application.mp4 76.3 MB
~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/50 - Building AXIS Slave Interface P2.mp4 65.5 MB
~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/52 - Building Complex FSM with existing FSM for AXIS.mp4 64.0 MB
~Get Your Files Here !/8 - Adding Master Interface/46 - Creating Master Interface with Vivado Template P2.mp4 62.7 MB
~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/60 - Building AXIS Slave Interface with Verilog P2.mp4 61.6 MB
~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/64 - Building AXIS Master Slave Interface with Verilog P1.mp4 57.5 MB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/39 - Modifying Delay of the Vivado Interrupt Template.mp4 55.3 MB
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/4 - Slave Lite Interface without I O Ports P1 Creating IP.mp4 55.3 MB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/29 - Adding Exisitng RTL COMPLEX FSM P1.mp4 54.7 MB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/11 - Adding Output port to Slave Lite Interface P1.mp4 50.3 MB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/15 - Adding Input and Output ports to Slave Lite Interface P2.mp4 49.3 MB
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/5 - Slave Lite Interface without I O Ports P2 Creating IP.mp4 49.3 MB
~Get Your Files Here !/1 - Section 0 Course Framework/2 - Course Framework.mp4 47.7 MB
~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/65 - Building AXIS Master Slave Interface with Verilog P2.mp4 45.1 MB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/14 - Adding Input and Output ports to Slave Lite Interface P1.mp4 44.8 MB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/26 - Add Existing RTL Delay Generator P2.mp4 43.8 MB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/28 - Adding Existing RTL Multiplier P2.mp4 43.3 MB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/40 - Generating Continuous Interrupt P1.mp4 41.5 MB
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/6 - Slave Lite Interface without I O Ports P3 Creating IP.mp4 39.2 MB
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/8 - Slave Lite Interface without I O Ports P5 Creating C Application.mp4 38.4 MB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/22 - Block Design used in Demonstration.mp4 38.0 MB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/12 - Adding Output port to Slave Lite Interface P2.mp4 37.1 MB
~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/59 - Building AXIS Slave Interface with Verilog P1.mp4 37.1 MB
~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/56 - Creating AXIS Master Interface P2.mp4 35.3 MB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/13 - Adding Output port to Slave Lite Interface P3.mp4 33.6 MB
~Get Your Files Here !/13 - Understanding Common Errors/69 - Common Error 2.mp4 24.8 MB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/18 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P1.mp4 24.5 MB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/19 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P2.mp4 24.0 MB
~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/61 - Building AXIS Slave Interface with Verilog P3.mp4 23.3 MB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/16 - Adding Input and Output ports to Slave Lite Interface P3.mp4 23.0 MB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/41 - Generating Continuous Interrupt P2.mp4 21.8 MB
~Get Your Files Here !/13 - Understanding Common Errors/68 - Common Error 1.mp4 19.1 MB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/20 - Understanding Mandatory Signal Master read from Slave (Reading Ops).mp4 12.0 MB
~Get Your Files Here !/1 - Section 0 Course Framework/1 - Interface Type.mp4 11.3 MB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/24 - Agenda.mp4 5.0 MB
~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/48 - Agenda.mp4 2.6 MB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/10 - Agenda.mp4 2.6 MB
~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/63 - Agenda.mp4 2.4 MB
~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/54 - Agenda.mp4 2.3 MB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/17 - Agenda.mp4 2.3 MB
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/3 - Agenda.mp4 2.3 MB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/35 - Agenda.mp4 2.1 MB
~Get Your Files Here !/8 - Adding Master Interface/44 - Agenda.mp4 2.1 MB
~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/58 - Agenda.mp4 2.0 MB
~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/30 - Agenda.mp4 1.9 MB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/37 - Using Vivado Interrupt Template Code P2 English.vtt 29.1 KB
~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/49 - Building AXIS Slave Interface P1 English.vtt 24.0 KB
~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/55 - Creating AXIS Master Interface P1 English.vtt 22.4 KB
~Get Your Files Here !/8 - Adding Master Interface/45 - Creating Master Interface with Vivado Template P1 English.vtt 21.3 KB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/42 - Blinking Effect with Interrupt English.vtt 18.7 KB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/36 - Using Vivado Interrupt Template Code P1 English.vtt 17.9 KB
~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/33 - Adding Interrupt with RTL P2 English.vtt 17.6 KB
~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/64 - Building AXIS Master Slave Interface with Verilog P1 English.vtt 17.2 KB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/25 - Add Existing RTL Delay Generator P1 English.vtt 15.7 KB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/23 - Analyzing Signals on ILA Probe English.vtt 15.4 KB
~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/31 - Fundamentals of Interrupt C Application English.vtt 14.5 KB
~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/32 - Adding Interrupt with RTL P1 English.vtt 13.7 KB
~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/60 - Building AXIS Slave Interface with Verilog P2 English.vtt 13.2 KB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/27 - Adding Existing RTL Multiplier P1 English.vtt 12.6 KB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/21 - Other Signals in Slave Lite Interface English.vtt 12.0 KB
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/7 - Slave Lite Interface without I O Ports P4 Creating C Application English.vtt 11.3 KB
~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/59 - Building AXIS Slave Interface with Verilog P1 English.vtt 11.0 KB
~Get Your Files Here !/Building Custom AXI Interface Peripherals for ZYNQ Devices.jpg 10.8 KB
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/4 - Slave Lite Interface without I O Ports P1 Creating IP English.vtt 10.1 KB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/29 - Adding Exisitng RTL COMPLEX FSM P1 English.vtt 10.0 KB
~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/52 - Building Complex FSM with existing FSM for AXIS English.vtt 9.7 KB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/18 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P1 English.vtt 8.5 KB
~Get Your Files Here !/1 - Section 0 Course Framework/2 - Course Framework English.vtt 8.4 KB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/39 - Modifying Delay of the Vivado Interrupt Template English.vtt 8.3 KB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/11 - Adding Output port to Slave Lite Interface P1 English.vtt 8.1 KB
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/5 - Slave Lite Interface without I O Ports P2 Creating IP English.vtt 7.9 KB
~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/50 - Building AXIS Slave Interface P2 English.vtt 7.6 KB
~Get Your Files Here !/8 - Adding Master Interface/46 - Creating Master Interface with Vivado Template P2 English.vtt 7.6 KB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/14 - Adding Input and Output ports to Slave Lite Interface P1 English.vtt 7.5 KB
~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/65 - Building AXIS Master Slave Interface with Verilog P2 English.vtt 7.2 KB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/19 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P2 English.vtt 6.6 KB
~Get Your Files Here !/Building Custom AXI Interface Peripherals for ZYNQ Devices.txt 6.5 KB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/40 - Generating Continuous Interrupt P1 English.vtt 6.1 KB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/26 - Add Existing RTL Delay Generator P2 English.vtt 5.9 KB
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/6 - Slave Lite Interface without I O Ports P3 Creating IP English.vtt 5.8 KB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/15 - Adding Input and Output ports to Slave Lite Interface P2 English.vtt 5.6 KB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/22 - Block Design used in Demonstration English.vtt 5.1 KB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/12 - Adding Output port to Slave Lite Interface P2 English.vtt 5.0 KB
~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/56 - Creating AXIS Master Interface P2 English.vtt 5.0 KB
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/8 - Slave Lite Interface without I O Ports P5 Creating C Application English.vtt 4.8 KB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/28 - Adding Existing RTL Multiplier P2 English.vtt 4.6 KB
~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/61 - Building AXIS Slave Interface with Verilog P3 English.vtt 4.6 KB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/13 - Adding Output port to Slave Lite Interface P3 English.vtt 4.2 KB
~Get Your Files Here !/13 - Understanding Common Errors/69 - Common Error 2 English.vtt 4.1 KB
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/20 - Understanding Mandatory Signal Master read from Slave (Reading Ops) English.vtt 3.9 KB
~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/53 - Code.html 3.3 KB
~Get Your Files Here !/13 - Understanding Common Errors/68 - Common Error 1 English.vtt 2.8 KB
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/16 - Adding Input and Output ports to Slave Lite Interface P3 English.vtt 2.7 KB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/41 - Generating Continuous Interrupt P2 English.vtt 2.7 KB
~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/67 - Code and BD.html 2.5 KB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/43 - Code.html 2.3 KB
~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/62 - Code and BD.html 2.1 KB
~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/34 - Code.html 2.1 KB
~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/66 - Code and BD.html 2.1 KB
~Get Your Files Here !/1 - Section 0 Course Framework/1 - Interface Type English.vtt 2.0 KB
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/38 - Code.html 1.8 KB
~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/24 - Agenda English.vtt 1.5 KB
~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/57 - Code.html 1.3 KB
~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/48 - Agenda English.vtt 974 bytes
~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/17 - Agenda English.vtt 964 bytes
~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/35 - Agenda English.vtt 945 bytes
~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/63 - Agenda English.vtt 917 bytes
~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/30 - Agenda English.vtt 899 bytes
~Get Your Files Here !/8 - Adding Master Interface/44 - Agenda English.vtt 792 bytes
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/9 - C Code.html 791 bytes
~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/54 - Agenda English.vtt 775 bytes
~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/51 - Code.html 775 bytes
~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/10 - Agenda English.vtt 746 bytes
~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/58 - Agenda English.vtt 613 bytes
~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/3 - Agenda English.vtt 583 bytes
~Get Your Files Here !/8 - Adding Master Interface/47 - Code.html 576 bytes
~Get Your Files Here !/Bonus Resources.txt 386 bytes
Get Bonus Downloads Here.url 182 bytes

[ DevCourseWeb.com ] Udemy - Building Custom AXI Interface Peripherals for ZYNQ Devices

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