|
SystemVerilog Design Start Programming Your Own ICs in HDL
2 weeks, 6 days
Files: 3 Total size: 540.1 MB Total requests: 22 Last access time: 2 days, 16 hours
|
Files: 1 Total size: 26.2 MB Total requests: 83 Last access time: 1 week, 3 days
|
|
Sutherland S. Verilog and SystemVerilog Gotchas...2007
6 months, 1 week
Files: 1 Total size: 6.6 MB Total requests: 140 Last access time: 1 hour, 50 minutes
|
Files: 4 Total size: 448.2 MB Total requests: 170 Last access time: 2 days, 18 hours
|
Files: 1 Total size: 5.2 MB Total requests: 171 Last access time: 6 days, 23 hours
|
Files: 3 Total size: 11.9 MB Total requests: 301 Last access time: 3 days, 20 hours
|
|
Дональд Томас - Логическое проектирование и верификация систем на SystemVerilog - 2019.pdf
1 year, 6 months
Files: 1 Total size: 4.5 MB Total requests: 1970 Last access time: 4 hours, 27 minutes
|
|
Learn SystemVerilog Assertions and Coverage Coding in-depth
1 year, 10 months
Files: 5 Total size: 745.0 MB Total requests: 851 Last access time: 10 hours, 2 minutes
|
Files: 1 Total size: 16.3 MB Total requests: 722 Last access time: 13 hours, 35 minutes
|